? semiconductor components industries, llc, 2002 april, 2002 rev. 4 1 publication order number: mc10e160/d mc10e160, mc100e160 5vecl 12bit parity generator/checker the mc10e/100e160 is a 12-bit parity generator/checker. the q output is high when an odd number of inputs are high. a high on the enable input (en ) forces the q output low. the 100 series contains temperature compensation. ? provides odd-high parity of 12 inputs ? shiftable output register with hold ? 900 ps max. d to q/q output ? enable ? asynchronous register reset ? dual clocks ? pecl mode operating range: v cc = 4.2 v to 5.7 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = 4.2 v to 5.7 v ? internal input pulldown resistors ? esd protection: > 1 kv hbm, > 75 v mm ? meets or exceeds jedec spec eia/jesd78 ic latchup test ? moisture sensitivity level 1 for additional information, see application note and8003/d ? flammability rating: ul94 code v0 @ 1/8o, oxygen index 28 to 34 ? transistor count = 312 devices device package shipping ordering information mc10e160fn plcc28 37 units/rail mc10e160fnr2 plcc28 500 units/reel mc100e160fn plcc28 37 units/rail mc100e160fnr2 plcc28 500 units/reel marking diagrams a = assembly location wl = wafer lot yy = year ww = work week plcc28 fn suffix case 776 mc10e160fn awlyyww mc100e160fn awlyyww 128 128 http://onsemi.com
mc10e160, mc100e160 http://onsemi.com 2 pin description pin function d 0 d 11 ecl data inputs s-in ecl serial data input en ecl enable, active low hold ecl hold, active low shift ecl shift, active high clk1, clk2 ecl clock inputs r ecl reset inputs q, q ecl direct output y, y ecl register output v cc , v cco positive supply v ee negative supply nc no connect logic diagram d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 8 d 9 d 10 en hold s-in shift clk1 clk2 r d 11 d r y y q 0 1 mux sel 0 1 mux sel d 1 d 11 hold s-in shift clk1 clk2 en v cco d 0 d 2 d 3 d 4 d 5 d 6 d 7 v ee d 8 d 9 d 10 26 27 28 2 3 4 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 567 8910 q q v cc y y v cco nc r 1 pinout: 28-lead plcc (top view) logic diagram and pinout assignment warning: all v cc , v cco , and v ee pins must be externally connected to power supply to guarantee proper operation. * all v cc and v cco pins are tied together on the die.
mc10e160, mc100e160 http://onsemi.com 3 maximum ratings (note 1) symbol parameter condition 1 condition 2 rating units v cc pecl mode power supply v ee = 0 v 8 v v ee necl mode power supply v cc = 0 v 8 v v i pecl mode input voltage v ee = 0 v v i v cc 6 v i c ode u o age necl mode input voltage ee 0 v cc = 0 v i cc v i v ee 6 6 v i out output current continuous surge 50 100 ma ma ta operating temperature range 0 to +85 c t stg storage temperature range 65 to +150 c q ja thermal resistance (junction to ambient) 0 lfpm 500 lfpm 28 plcc 28 plcc 63.5 43.5 c/w c/w q jc thermal resistance (junction to case) std bd 28 plcc 22 to 26 c/w v ee pecl operating range necl operating range 4.2 to 5.7 5.7 to 4.2 v v t sol wave solder <2 to 3 sec @ 248 c 265 c 1. maximum ratings are those values beyond which device damage may occur. 10e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 82 98 82 98 82 98 ma v oh output high voltage (note 2) 3980 4070 4160 4020 4105 4190 4090 4185 4280 mv v ol output low voltage (note 2) 3050 3210 3370 3050 3210 3370 3050 3227 3405 mv v ih input high voltage 3830 3995 4160 3870 4030 4190 3940 4110 4280 mv v il input low voltage 3050 3285 3520 3050 3285 3520 3050 3302 3555 mv i ih input high current clk1, clk2 r all other inputs 200 300 150 200 300 150 200 300 150 m a m a m a i il input low current 0.5 0.3 0.5 0.25 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 82 98 82 98 82 98 ma v oh output high voltage (note 2) 1020 930 840 980 895 810 910 815 720 mv v ol output low voltage (note 2) 1950 1790 1630 1950 1790 1630 1950 1773 1595 mv v ih input high voltage 1170 1005 840 1130 970 810 1060 890 720 mv v il input low voltage 1950 1715 1480 1950 1715 1480 1950 1698 1445 mv i ih input high current clk1, clk2 r all other inputs 200 300 150 200 300 150 200 300 150 m a m a m a i il input low current 0.5 0.3 0.5 0.065 0.3 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.06 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts.
mc10e160, mc100e160 http://onsemi.com 4 100e series pecl dc characteristics v ccx = 5.0 v; v ee = 0.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 82 98 82 98 94 113 ma v oh output high voltage (note 2) 3975 4050 4120 3975 4050 4120 3975 4050 4120 mv v ol output low voltage (note 2) 3190 3295 3380 3190 3255 3380 3190 3260 3380 mv v ih input high voltage 3835 4050 4120 3835 4120 4120 3835 4120 4120 mv v il input low voltage 3190 3300 3525 3190 3525 3525 3190 3525 3525 mv i ih input high current clk1, clk2 r all other inputs 200 300 150 200 300 150 200 300 150 m a m a m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts. 100e series necl dc characteristics v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 82 98 82 98 94 113 ma v oh output high voltage (note 2) 1025 950 880 1025 950 880 1025 950 880 mv v ol output low voltage (note 2) 1810 1705 1620 1810 1745 1620 1810 1740 1620 mv v ih input high voltage 1165 950 880 1165 880 880 1165 880 880 mv v il input low voltage 1810 1700 1475 1810 1475 1475 1810 1475 1475 mv i ih input high current clk1, clk2 r all other inputs 200 300 150 200 300 150 200 300 150 m a m a m a i il input low current 0.5 0.3 0.5 0.25 0.5 0.2 m a note: devices are designed to meet the dc specifications shown in the above table, after thermal equilibrium has been establishe d. the circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 1. input and output parameters vary 1:1 with v cc . v ee can vary +0.46 v / 0.8 v. 2. outputs are terminated through a 50 ohm resistor to v cc 2 volts.
mc10e160, mc100e160 http://onsemi.com 5 ac characteristics v ccx = 5.0 v; v ee = 0.0 v or v ccx = 0.0 v; v ee = 5.0 v (note 1) 0 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit f max maximum toggle frequency tbd tbd tbd ghz t plh propagation delay to output ps t phl d to q 400 650 950 400 650 950 400 650 950 en to q 300 550 750 300 550 750 300 550 750 clk to y 275 500 700 275 500 700 275 500 700 r to y 275 500 725 275 500 725 275 500 725 t s setup time ps d 1200 900 1200 900 1200 900 hold 600 300 600 300 600 300 s-in 350 150 350 150 350 150 shift 500 250 500 250 500 250 t h hold time ps d 400 900 400 900 400 900 hold 100 300 100 300 100 300 s-in 300 150 300 150 300 150 shift 200 250 200 250 200 250 t jitter cycletocycle jitter tbd tbd tbd ps t r rise/fall time ps t f (20 - 80%) 300 450 650 300 450 650 300 450 650 1. 10 series: v ee can vary +0.46 v / 0.06 v. 100 series: v ee can vary +0.46 v / 0.8 v. figure 1. typical termination for output driver and device evaluation (see application note and8020 termination of ecl logic devices.) driver device receiver device qd 50 50 v tt q d v tt = v cc 2.0 v
mc10e160, mc100e160 http://onsemi.com 6 resource reference of application notes an1404 eclinps circuit performance at nonstandard v ih levels an1405 ecl clock distribution techniques an1406 designing with pecl (ecl at +5.0 v) an1503 eclinps i/o spice modeling kit an1504 metastability and the eclinps family an1568 interfacing between lvds and ecl an1596 eclinps lite translator elt family spice i/o model kit an1650 using wireor ties in eclinps designs an1672 the ecl translator guide and8001 odd number counters design and8002 marking and date codes and8020 termination of ecl logic devices
mc10e160, mc100e160 http://onsemi.com 7 package dimensions plcc28 fn suffix plastic plcc package case 77602 issue e 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.010 (0.250) tl -m s n s s 0.007 (0.180) tl -m s n s m 0.007 (0.180) tl -m s n s m 0.004 (0.100) seating plane -t- 12.32 12.32 4.20 2.29 0.33 0.66 0.51 0.64 11.43 11.43 1.07 1.07 1.07 2 10.42 1.02 12.57 12.57 4.57 2.79 0.48 0.81 11.58 11.58 1.21 1.21 1.42 0.50 10 10.92 1.27 bsc a b c e f g h j k r u v w x y z g1 k1 min min max max inches millimeters dim notes: 1. datums l, m, and n determined where top of lead shoulder exits plastic body at mold parting line. 2. dim g1, true position to be measured at datum t, seating plane. 3. dim r and u do not include mold flash. allowable mold flash is 0.010 (0.250) per side. 4. dimensioning and tolerancing per ansi y14.5m, 1982. 5. controlling dimension: inch. 6. the package top may be smaller than the package bottom by up to 0.012 (0.300). dimensions r and u are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash, but including any mismatch between the top and bottom of the plastic body. 7. dimension h does not include dambar protrusion or intrusion. the dambar protrusion(s) shall not cause the h dimension to be greater than 0.037 (0.940). the dambar intrusion(s) shall not cause the h dimension to be smaller than 0.025 (0.635). view s b u z g1 x view d-d h k f view s g c z a r e j 0.485 0.485 0.165 0.090 0.013 0.026 0.020 0.025 0.450 0.450 0.042 0.042 0.042 2 0.410 0.040 0.495 0.495 0.180 0.110 0.019 0.032 0.456 0.456 0.048 0.048 0.056 0.020 10 0.430 0.050 bsc -n- y brk d d w -m- -l- 28 1 v g1 k1
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